1. Field of the Invention
The present invention relates to a decoder which is adapted to receive the dialing or keying signals which are transmitted over telephone systems, and similar selective signaling systems, and is settable to recognize any preselected sequence or code of dialed numbers and produce a corresponding output recognition signal. The invention relates particularly to such a decoder which utilizes counters in its decoding circuitry which are mechanized with complementary semi-conductor circuitry and further utilizes in conjunction with such counters a novel and unique control switching circuit for ordering the reset of a counter whenever a number sequence differing from the preselected code is received.
2. Description of the Prior Art
Telephone decoders are used in a wide variety of selective signaling applications, as for example in the receivers of two-way radio-telephone networks or two-way radio communication systems and also in party line telephone signaling. In such communication networks, communication between a central transmitter and any desired remote receiver is often established by transmitting a common tone signal to all receivers. In order to address or dial a selected one of those receivers, the transmitter tone is interrupted to represent the sequential digits of the telephone number or code number of the desired remote receiver. The decoder in that receiver is preset to recognize that particular pattern of tone interruptions as its preset digit sequence, and responds by producing an output recognition signal which may be used to sound a horn or buzzer, light a signaling light, or otherwise activate some output device. The receiver operator can then respond and acknowledge to the transmitter that he is available to receive a message on the common transmission link, and the two-way communciation process is thereby begun. During the same period that the decoder in the selected receiver recognizes that it has received its correct dialed code, the respective decoders in all other receivers recognize that they have received an incorrect dialed code and are thereby reset to their initial starting or monitoring states. Customarily after message transmission has been completed, the sending transmitter may switch off its tone signal and this normally has the effect of assuring resetting of all the decoders in the remote receivers to their initial or monitoring states, so that they can perform properly when the tone is switched on again at a later time for the transmission of another dialing select.
Consider for example, a conventional radio-telephone signaling system in which a central transmitter desires to communicate with a particular receiver which has the code number 324. To do this, the transmitter begins to transmit a tone signal and then begins to interrupt that tone signal in a pattern of interrupts sequentially representing the digits 3, 2, and 4. Such a pattern of interrupts in the conventional telephone code is first a series of three interrupts, then a pause, then a series of two interrupts, then a pause, then a series of four interrupts, and then a pause to thereby complete the representation of the code number 324. This pattern of interrupts is recognized by the decoder in receiver No. 324. which then responds by producing a recognition signal to activate a buzzer, light, etc. The operator of the receiver then picks up his phone, indicates that he is receiver 324 answering the call, and a two-way communication is then conducted. During the same period the decoder in receiver 324 was recognizing the interrupt pattern as being its own code number, the decoders in the other non-selected receivers recognized that the interrupt pattern did not represent their respective code numbers and were thereby reset to their starting positions. The decoder in the selected receiver is later reset either by the cessation of the tone signal after the completion of dialing or by the reception of some additional number sequence which does not correspond with its code setting.
Continuing with the description of such a conventional prior art, radio telephone signaling system, in the receiver decoder the incoming tone signal with its dialed tone interrupts is operated upon by the tone processing circuitry to produce so called digit pulses and interdigit pulses. A single digit pulse is produced in response to each tone interrupt so that an incoming code 324 would occasion the production first of a sequence of three digit pulses constituting a first digit set representing the digit 3, then a pause, then a sequence of two digit pulses constituting a second digit set representing the digit 2, then another pause, then a sequence of four digit pulses constituting a third digit set, representing the digit 4 of the code number 324, and then a final pause. An interdigit pulse is produced during each of the aforesaid pauses, each starting a predetermined time after the occurrence of the last pulse of the preceding digit set and normally being terminated by the occurrence of the first digit pulse of the next digit. Thus, in response to the incoming code 324, three interdigit pulses would be produced by the tone processing circuitry, spaced apart in the pause following the digit sets. The tone processing circuitry may also produce a separate tone presence signal which represents the overall presence or absence of the applied incoming tone signal or alternatively it may use the digit pulses for the same type of indication.
The digit pulses and interdigit pulses are then operated upon by discrete or digital decoding circuitry to recognize only those digit sequences which correspond to the internal code which has been preset in the digital decoding circuitry. Such recognition or decoding operations are ordinarily accomplished through cooperative usage of two counters. The first counter may be termed a digit pulse counter and it counts how many digit pulses occur in each digit set, and then is reset after the digit set by the following interdigit pulse. The second counter may be termed an interdigit pulse counter and it counts each interdigit pulse received so long as each such interdigit pulse is preceded by a "correct" digit set. If an interdigit pulse is not preceded by a correct digit set, then the interdigit pulse counter will not count the following interdigit pulse but will instead be reset at that time to its starting position. Thus, (assuming that code number 324 is the correct code number) the digit pulse counter will be able to attain count of 3 only if each of the correct digit sets 3, 2, and 4 are received in that order. The fact that the interdigit pulse counter has attained a count of 3 can therefore be used as an indication or recognition that the correct code number has been received and the counter state may therefore be used to produce an output recognition signal of the decoder for the purpose of energizing external signaling devices.
The manner in which the two counters are utilized to operate upon the digit pulses and interdigit pulses so as to recognize the preset code can be further clarified by briefly considering the numerical example which is set forth in Table 1 below.
TABLE 1 __________________________________________________________________________ Operation of Decoder Set to Recognize Code Number 324 __________________________________________________________________________ TIME Sequence of (1st digit set) (2nd digit set) (3rd digit set) Digit Pulses- 1 1 1 1 1 1 1 1 1 Sequence of Interdigit Pulses- 1 1 1 Count of Digit Pulse Counter- 0 1 2 3 0 1 2 0 1 2 3 4 0 Count Of Interdigit Pulse Counter- 0 0 0 0 1 1 1 2 2 2 2 2 3 __________________________________________________________________________
Assuming once again that the correct, code number is 324, the first line of Table 1 entitled `Sequence of Digit Pulses` shows a sequence of three 1's then a space then two 1's then a space then four 1's and a space, representing, in a stylized manner, the time occurrence of the digit pulses in the three digit sets representing the code number 324. The line entitled `Sequence of Interdigit Pulses` shows three 1's, each representing the production of an interdigit pulse during the pauses following the first, second and third digit sets. The remaining lines show the count states successively obtained by the digit pulse counter and by the interdigit pulse counter in response to their reception of the indicated digit pulses of the first line of Table 1 and the interdigit pulses of the second line of Table 1. It can be seen, referring to Table 1, that initially both counters are assumed to be in their zero count states. Then the three successive pulses of the first digit set are received and the digit pulse counter counts them so as to advance step by step to a count of three. No interdigit pulse has yet been received so that the interdigit pulse counter remains at the same time in its zero count state.
As shown in Table 1 in response to the first interdigit pulse, the digit pulse counter is reset to its zero state and at the same time the interdigit pulse is counted by the interdigit pulse counter (because the interdigit pulse has been preceded by a correct digit set) and the interdigit pulse counter is thereby advanced to a count of 1 in response to the first digit set.
As indicated in Table 1 the same operations are repeated again in response to the pulses of the second digit set and to the second interdigit pulse, so that interdigit pulse counter is thereby advanced to a count of 2 in response to the second interdigit pulse. In the same manner in response to the digit pulses of the third digit set and to the third interdigit pulse, the interdigit pulse counter is advanced to a count of 3 in response to the third interdigit pulse.
The fact that the interdigit pulse counter has attained a count of 3 indicates that the correct code number has been received, because otherwise the interdigit pulse counter would have been reset to its zero count during the process and would therefore never have been able to reach its final attained count of 3. Thus, for example, if an incorrect code 224 was received so that the first digit set had only two digit pulses representing an "incorrect" digit 2 rather than the correct digit 3, the interdigit pulse counter would have been reset by the first interdigit pulse rather than being advanced by it to a count of 1. Because of such reset, the interdigit pulse counter would never have obtained a final count of 3 in response to the incorrect code number 224. Thus, it is clear that the attainment by the interdigit pulse counter of the count of 3 is a reliable indicator that the correct code number has been received and can be used to generate a suitable recognition signal.
It should be recognized that a conventional counter has a series of output lines or conductors which can be designated as its `0`, `1`, `2`, etc. output lines which are selectively energized in accordance with the attained count of the counter. Thus, for example, a counter may energize its `5` output line, whenever the counter attains a corresponding count of 5. Each of the other output lines of a counter is energized in the same manner when the counter reaches the corresponding count level.
With this understanding referring to Table 1 it is easy to understand how the control circuitry of a conventional decoder is able to use the digit counter and the interdigit counter, to recognize that a correct digit set has been received and thereby determine whether or not the immediately following interdigit pulse shall be used to advance the interdigit pulse counter (for a correct digit set) or be used instead to reset the interdigit pulse counter (for an incorrect digit set). The decoder control circuitry can effect such recognition by pairing preselected output lines of the two counters and comparing the output voltage levels of the paired output lines for match or disagreement in output energization. For example, referring to Table 1, it is seen that at a time just before the first interdigit pulse arrives, the count of the digit pulse counter should be 3, and the count of the interdigit pulse counter should be 0. Thus, the control circuitry of the decoder can determine what action to take in response to the first interdigit pulse by merely comparing the voltage of the `0` output line of the interdigit pulse counter with the `3` output line of the digit pulse counter. If the voltages of these two output lines are in agreement, this indicates that the first digit set received was a correct digit set and therefore the immediately following interdigit pulse is used to advance the count of the interdigit pulse counter from 0 to 1. Similarly, at the time that the second interdigit pulse arrives, the control determination can be made by comparing the voltages of the `1` output line of the interdigit pulse counter with the `2` output line of the digit pulse counter and advancing or resetting the interdigit pulse counter in accordance with the agreement or disagreement of the output voltages of these two lines. Finally, in response to the third interdigit pulse, the control determination can be made by comparing the output voltages on the `2` output line of the interdigit pulse counter with the `4` output line of the digit pulse counter. If agreement is found between these two output lines, the interdigit pulse counter is advanced to its count of 3 so that its `3` output line is thereby energized by a predetermined voltage. This energization of the `3` output line can be utilized as the required output recognition signal which indicates that the correct code number has been received.
It is evident, therefore, that the presetting of a particular code number in a conventional prior art docoder may be accomplished by providing a plurality of conventional logic gate comparison circuits, each of which may be connected or "strapped" between the appropriate preselected pairs of output wires of the digit pulse counter and the interdigit pulse counter. Each such logic gate is adapted to produce a voltage output corresponding to agreement or disagreement of the counter output leads between which it is interconnected or strapped. The output voltages of all the comparison logic gates are summed in an "or" logic function in a second logic circuit and applied to actuate a transistor switch in accordance with agreement or disagreement of any of the pairs of strapped or interconnected output lines.
A difficulty which is presented in such prior art decoders is that the use of two sets of logic gates for the comparison and summing functions entails a very high parts count for the many semi-conductors and resistances of the logic gates. In addition, in some types of logic gates very precise resistor values may be required. More important, because of the need for summing the outputs of all of the individual logic comparison gates, difficulty is presented with leakage currents and sneak currents which reduce the operating margins of the logic gates and limit the range of operating voltages of the circuit in which satisfactorily reliable operation can be obtained. The high cost, high parts count, and limited operating range of the logic gate system of comparing the output voltages of strapped pairs of counter leads represents a relatively serious deficiency of prior art decoders of the type described.